The present invention relates to a fabrication technique for a semiconductor memory and, in particular, to technique effectively applied to a semiconductor memory, semiconductor testing equipment therefor, a testing method thereof, and a fabrication method thereof.
In recent years, advancement is made of a speed-up and a high-capacity memory represented by a DRAM. In the high-speed memory, a SDRAM (Synchronous DRAM) that executes a read/write operation to the memory in synchronization with a clock has become a mainstream. Quite recently, there to a SDRAM with a DDR (Double Data Rate), in which data is outputted in synchronization with both of a rising edge and a falling edge of the clock. For this reason, a data transmission rate thereof is doubled without increasing a clock frequency, whereby an operation having a further higher rate than a current rate of 266 to 333 Mbps has become possible.
Furthermore, in the high-capacity memory, by the DRAM characterized in that only a single transistor is used in a memory cell, the high-capacity memory having several gigabits through 512 Mbits from 256 Mbits becomes a mainstream increasingly. Further, an important factor other than the factors of the high speed and capacity of the memory is to make a price of the memory lower. A market competition of the memory is in a dead heat state, and respective companies give special emphases on making the price of the memory lower. In a semiconductor testing equipment for testing such memories, it is desired to reduce a cost of testing together With fulfillment of needs of the high speed and capacity of the memory. It is indispensable to make lower the price of the semiconductor testing equipment for testing the memory in order to reduce the cost of testing. It is effective to increase integration of LSIs constituting the memory testing equipment and downsize the apparatus in order to make the cost of testing lower.
Furthermore, in fabrication of the memory, even if there is a defect in one memory cell constituting the memory, the entirety of a memory chip is regarded as a defective one. However, since a ratio at which the defect is found in one memory chip increases due to the high capacity of the memory, a fabrication yield is decreased due to the high capacity thereof and making the price of the memory lower becomes difficult. Consequently, preliminary memory cells (redundant cells) are normally found in the same memory chip in advance in addition to the memory cells which are originally used at the time of fabricating the memory. In the case where any defective memory cells are found, a decrease in the yield in the fabrication is prevented by executing a redundancy processing for replacing the defective memory cells with the preliminary memory cells.
Such a redundancy processing is generally performed by detecting a defective cell address by a probe inspection in a wafer level of a semiconductor and replacing the defective cell with a redundant cell. For example, Japanese Patent Laid-open No. 2003-132697 discloses a technique in which, in the testing of the memory such as a DRAM, data of “1” or “0” is written into an arbitrary address of the memory and the data is read from the address to be compared to the written data (expected value) and then determines whether the memory is normal. At this time, if the data written into the memory and the data read from the memory are inconsistent with each other in at least one item obtained from a comparison result, it is judged that the whole memory is a defective. However, it is required to memorize information of the memory cell (FBM: Fail Bit Map) which has been defect (failed) in order to perform the redundancy processing. This FBM information is stored in the fail memory as a result of testing of a memory under test.